The present invention relates generally to comparator circuits and, more particularly, to a comparator circuit with improved symmetry in operation.
In many data channels, a digital sample is created by "level-slicing" (also referred to as "data slicing") whereby digital level signals are generated by using a fast comparator to compare the analog input signal to a reference voltage level. The goal in some data channel applications (such as in Compact Disc ("CD") channels) is to accurately generate a digital signal based on zero crossing times. Thus, the transition times of the digital signal should be an accurate reflection of the zero-crossing times of the analog input waveform. (Note that the absolute delay between analog zero-crossing time and digital signal transition time is not of significant importance.) This issue becomes increasingly critical in CD-ROM applications where the raw channel data rates have been increasing from 4.3218 Mb/s (when first introduced) to conceivably greater than 150 Mb/s in the foreseeable future.
FIG. 1 illustrates an ideal, noninverting comparator 100 with an Analog Input path 102, an analog reference voltage ("Vref") input path 106, and a Digital Output path 104. FIG. 2 illustrates the ideal operation of comparator 100 with zero volts (0V) applied to input 106 as Vref. In operation, the Analog Input voltage is compared to Vref. The output voltage should be a digital representation of the polarity of the Analog Input (e.g., if the input voltage is higher than Vref, the output is a logical "1" and conversely, if the input voltage is lower than Vref, the output is a logical "0"). Preferably, the relative zero-crossing times of the analog input are preserved in the Digital Output. Thus, referring to Analog Input waveform 202 and Digital Output waveform 204 of FIG. 2, the equalities as set out in equations (1) through (4) are sought: EQU at1=dt1 (1) EQU at2=dt2 (2) EQU at3=dt3 (3) EQU atx=dtx (4)
where x=4,5, etc.
Waveforms 202 and 204 are shown slightly skewed from each other in FIG. 2 due to the absolute delay 206 between analog zero-crossing time and digital signal transition time.
Numerous existing designs attempt to satisfy the equalities of equations (1)-(4). However, they all suffer from jitter (i.e., unmatched rise and fall times of the Digital Output) due to, among other things, input amplitude variations and input slew variations. These input variations affect the delay time through the comparator by creating unmatched (i.e., asymmetric) delays in response to rising and falling transitions of input signals. This problem is particularly acute for high data-rate channels since any jitter (due to asymmetric delays through the comparator) becomes a more significant fraction of the data pulse width and therefore results in a higher data error rate. Furthermore, when implementing this function in state of the art CMOS technologies that require a low supply voltage (i.e., +3.3 v), this problem becomes further exacerbated and therefore even more difficult to correct.
An exemplary inverting comparator circuit 300 known in the art is provided in FIG. 3A. Circuit 300 is implemented in CMOS technology which, as is well known, includes PMOS transistors (i.e., MOS transistors having P-type source/drain regions in N-type substrate) and NMOS transistors (i.e., MOS transistors having N-type source/drain regions in P-type substrate regions). Of course, it will be understood that a transistor symbol with a circle on the gate represents a PMOS transistor and a transistor symbol without a circle on the gate represents an NMOS transistor. The power supply voltage in this circuit is denoted as VDD, which is typically at approximately +5.0 volts or lower (i.e., +3.3 volts). The ground potential in this circuit is denoted as VSS, which is typically at zero volts. In passing, it should be noted that the foregoing symbols and abbreviations apply to all other figures contained herein.
Circuit 300 includes an input differential pair made up of NMOS transistors 302, 304. Analog Input on input path 320 and Vref on input path 322 are coupled to the gates of transistors 302 and 304, respectively. The sources of these transistors are coupled to current source 362 which is, in turn, coupled to VSS. The drain of NMOS transistor 304 is also coupled to current source 364 which is, in turn, coupled to VSS. This drain is also coupled to a current mirror made up of PMOS transistors 314 and 316. Similarly, the drain of NMOS transistor 302 is coupled to current source 360 which is, in turn, coupled to VSS. This drain is further coupled to a second current mirror made up of PMOS transistors 310 and 312.
As shown in FIG. 3A, the sources of transistors 310-316 are coupled to VDD. The drain of PMOS transistor 310 is coupled to the drain of NMOS transistor 306. Transistor 306 with NMOS transistor 308 form a third current mirror in comparator circuit 300. As shown in this figure, the sources of NMOS transistors 306 and 308 are coupled to VSS.
Transistors 316 and 308 form an output stage of circuit 300. In this stage, PMOS transistor 316 functions as a current-sourcing (or current-charging) transistor and NMOS transistor 308 functions as a current-sinking (or current discharging) transistor. Digital Output on output 324 is an inverted digital representation of the polarity of the Analog Input; i.e., when Analog Input is greater than Vref, Digital Output is a logical "0" and when Analog Input is less than Vref, Digital Output is a logical "1".
There are many ways of converting an inverting comparator (like circuit 300) to a noninverting comparator, one of which is by adding an inverter. For example, circuit 300 may be converted to a noninverting comparator by coupling an inverter to output 324. A conventional CMOS inverter 370 containing a PMOS transistor 376 and NMOS transistor 374 is illustrated in FIG. 3B. As shown therein, the gates and drains of transistors 376, 374 are tied together to form input 372 and output 378, respectively. Further, the sources of transistors 376 and 374 are coupled to VDD and VSS, respectively. Coupling output 324 to inverter input 372 would convert circuit 300 into a noninverting comparator with a new output 378.
Referring again to FIG. 3A, current sources 360 and 364 are added to improve circuit speed (i.e., by keeping PMOS transistors 312 and 314, respectively, in a conducting or "ON" state), but are not critical for circuit operation.
In operation, circuit 300 exhibits three fundamental problems. First, input differential pair 302,304 inherently does not operate in a truly differential manner. Input path 322 receives a DC (i.e., non-oscillating) reference voltage (e.g., zero volts) while input path 320 receives a varying (i.e., oscillating) analog voltage. Such disparate inputs lead to asymmetrical delays between rising and falling input transitions producing output signal degradation in the form of jitter.
Second, falling and rising edge paths have different delay paths to output 324. When input path 320 receives a rising transition, current is steered through NMOS transistor 302, mirrored through PMOS transistors 310 and 312, and finally mirrored through NMOS transistors 306 and 308. Hence, the delay path for responding to a rising edge signal includes differential input transistor 302 and two current mirrors. However, a falling transition causes current to be steered through NMOS transistor 304 and mirrored through PMOS transistors 314 and 316. Accordingly, the delay path for responding to a falling edge signal includes differential input transistor 304 and only one current mirror. These differing signal paths will exhibit asymmetric delays which further contributes to jitter in the output signal.
Third, circuit 300 introduces additional jitter to Digital Output when a low power supply is used and the analog input waveform has a high amplitude. As an example, consider the case where a supply voltage VDD of 3.3V is used and the input swings between 0.7V and 3.5V. When current is steered through transistor 302, this transistor will undesirably transition from saturation mode to triode (linear) mode. Transistor 304, however, will always be in saturation mode. The resulting differences in the operation of each transistor presents another asymmetry in delays for a rising versus a falling input edge.
Accordingly, a comparator is desired that serves to reduce or eliminate asymmetry in its operation, like that described above, and thereby produce a more accurate output signal.